For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
In semiconductor devices such as DRAMs (Dynamic Random Access Memory), each cell is composed of one transistor and one capacitor. In DRAMs, cells require periodic reading and refreshing. Owing to the advantages of low price-per-unit-bit, high integration, and ability to simultaneously perform read and write operations, DRAMs have enjoyed widespread use in commercial applications. In the meantime, a phenomenon referred to as “soft error” can be caused in DRAM devices by a loss of charge that was stored in a capacitor due to external factors, thereby causing malfunction of DRAMs. In order to prevent the occurrence of soft error, a method of enhancing the capacitance of a capacitor has been suggested. However, challenges are presented in formulating practical manufacturing processes due to the ever increasing high level of integration of semiconductor devices.
Furthermore, metal lines are typically integrated in layers separate from capacitor layers. In an example, a copper metal layer is formed above a group of capacitors and is not run in the same layer as the capacitors. FIG. 1 represents such an example where vias of metal lines are formed through capacitor dielectric layers to connect the upper metal line layers to lower device layers. Specifically, FIG. 1 is a cross-sectional view of a capacitor formed in a dielectric layer distinct from a dielectric layer used to house metal wiring, in accordance with the prior art.
Referring to FIG. 1, a first interlayer insulating layer 103 is formed on a semiconductor substrate 101 having a cell array region 102. The first interlayer insulating layer 103 is patterned to form contact holes exposing the semiconductor substrate 101 on the cell array region 102 and the contact holes are filled with a conductive material to form a lower electrode contact plug 105A. An etch stop layer 107 and a second interlayer insulating layer 109 are sequentially formed on the resulting structure.
The second interlayer insulating layer 109 and the etch stop layer 107 are sequentially etched in the cell array region 102 to form the lower electrode contact plug 105A and a storage node hole 111 exposing the first interlayer insulating layer 103 around the lower electrode contact plug. After a material layer for a lower electrode is conformally stacked on the resulting structure, a planarization process is carried out to form the lower electrode 113 covering a bottom and an inner sidewall of the storage node hole 111. A dielectric layer 115 and an upper electrode layer 117 are sequentially stacked and patterned on the semiconductor substrate 101. A via 124 of a metal line 122 is formed through capacitor dielectric layers (e.g., dielectric layer 109, and even inter-layer dielectric layer 120) to connect the upper metal line 122 layer to the semiconductor substrate 101 having the cell array region 102.